/*
 * File   : top_bench.v
 * Date   : 20171106
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module top_bench();

// CLK

// RST

// MAIN
reg phy_giga_mode;
reg phy_link_up;
initial                                                
begin                                             
    $display("Testbench running!");
	
	top_bench.phy_giga_mode = 1'b1;
	top_bench.phy_link_up   = 1'b0;
	#2000;
	top_bench.phy_link_up   = 1'b1;
end

// PHY RGMII: signal naming from DUT point of view
wire       RxClk;
wire       RxDv;
wire [3:0] RxData;
wire       TxClk;
wire       TxEn;
wire [3:0] TxData;
phy_rgmii_bfm bfm_rgmii (
    .RxClk  (RxClk),
    .RxDv   (RxDv),
    .RxData (RxData),
    .TxClk  (TxClk),
    .TxEn   (TxEn),
    .TxData (TxData)
);
//// RGMII loopback for BFM
//assign {TxClk, TxEn, TxData} = {RxClk, RxDv, RxData};

// DUT
wire         gen_en     ;
wire [31: 0] int_data_i ;
wire         int_valid_i;
wire         int_sop_i  ;
wire         int_eop_i  ;
wire [ 1: 0] int_mod_i  ;

wire         par_en     ;
wire [31: 0] int_data_o ;
wire         int_valid_o;
wire         int_sop_o  ;
wire         int_eop_o  ;
wire [ 1: 0] int_mod_o  ;

mac_top dut (
    .rst(!phy_link_up),
    .clk(RxClk),
	
	.phy_giga_mode(phy_giga_mode),  
	
    .gen_en       ( gen_en      ),  //output reg 
    .int_data_i   ( int_data_i  ),  //input  wire [31: 0] 
    .int_valid_i  ( int_valid_i ),  //input  wire         
    .int_sop_i    ( int_sop_i   ),  //input  wire         
    .int_eop_i    ( int_eop_i   ),  //input  wire         
    .int_mod_i    ( int_mod_i   ),  //input  wire [ 1: 0]

    .par_en       ( par_en      ),  //output reg
    .int_data_o   ( int_data_o  ),  //output reg  [31: 0] 
    .int_valid_o  ( int_valid_o ),  //output reg          
    .int_sop_o    ( int_sop_o   ),  //output reg          
    .int_eop_o    ( int_eop_o   ),  //output reg          
    .int_mod_o    ( int_mod_o   ),  //output reg  [ 1: 0]

    `ifdef ENABLE_INTERNAL_PHY
    .gmii_rxclk (),  //input  wire          
    .gmii_rxctrl(),  //input  wire          
    .gmii_rxdata(),  //input  wire [ 7: 0]  
    .gmii_txclk (),  //output wire          
    .gmii_txctrl(),  //output wire          
    .gmii_txdata()   //output wire [ 7: 0]  
    `else
    .rgmii_rxclk (RxClk ),  //input  wire         
    .rgmii_rxctrl(RxDv  ),  //input  wire         
    .rgmii_rxdata(RxData),  //input  wire [ 3: 0] 
    .rgmii_txclk (TxClk ),  //output wire         
    .rgmii_txctrl(TxEn  ),  //output wire         
    .rgmii_txdata(TxData)   //output wire [ 3: 0] 
    `endif

);

// streaming loopback
assign {int_data_i, int_valid_i, int_sop_i, int_eop_i, int_mod_i} = {int_data_o, int_valid_o, int_sop_o, int_eop_o, int_mod_o};


endmodule

